1. Field of the Invention
The present invention relates to a semiconductor device suitable for use as a dynamic random access memory (DRAM) stacked with a multi-core central processing unit (CPU) or the like, and a control method thereof.
Priority is claimed on Japanese Patent Application No. 2010-1981, filed Jan. 7, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
A technique is proposed to implement high speed by dividing a DRAM array so as to use the DRAM three-dimensionally (3D) stacked with a CPU as a cache. This technique is disposed by A. Vignon, S. Cosemans, W. Dehaene, P. Marchal and M. Facchini, in “A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context,” Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09. 20-24 Apr. 2009, pp. 929-933.
A pipelined operation using a two-transistor (2T) type DRAM is proposed as a method of improving a DRAM operation cycle suitable for the 3D stack or the like. This operation is disclosed by SOMASEKHAR Dinesh, Y E Yibin, ASERON Paolo, L U Shih-Lien, KHELLAH Muhammad, HOWARD Jason, RUHL Greg, KARNIK Tanay, BORKAR Shekhar, D E Vivek, KESHAVARZI Ali, in “2 GHz 2 Mb 2T Gain-Cell Memory Macro With 128 GB/s Bandwidth in a 65 nm Logic Process,” Solid-State Circuits Conference 2008 (ISSCC 2008), SESSION 14, EMBEDDED & GRAPHOCS DRAMs/14.3, Digest of Technical Papers, pp. 274-275, Feb. 5, 2008. A DRAM macro disclosed in Non-patent Document 2 is constituted as a 2 Mb macro using eight 256 Kb (bit) arrays in which an independent operation is performed. Here, the DRAM macro is a functional block integrated in a type in which a DRAM circuit function can be combined with other circuit functions. Input/output (I/O) has a configuration of 8×64×2=1 K, and a 1-array configuration is 128 Rows×4 Columns×64 I/O×8 Banks. A random cycle is 4 ns=8 clocks, and a 4-stage pipeline operation in which 2 banks of the 8 banks are used for each stage is performed. A read/write separation bus is used.